The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of lightly-doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high-speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current of the transistor adversely impact leakage current.
Metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion. However, simply replacing polysilicon gate electrodes with metal gate electrodes may engender issues in forming the metal gate electrode prior to high-temperature annealing to activate the source/drain implants, such as at temperatures in excess of 900° C. Such fabrication techniques may degrade the metal gate electrode or cause interaction with the gate dielectric layer, thereby adversely impacting transistor performance.
Replacement gate techniques have been developed to address problems attendant upon substituting metal gate electrodes for polysilicon gate electrodes. For example, a polysilicon gate is used during initial processing until high temperature annealing to activate source/drain implants has been implemented. Subsequently, the polysilicon is removed and replaced with a metal gate.
An initial step in fabricating this “replacement metal gate” is the formation of an interfacial oxide layer to serve as a barrier between the silicon substrate and the replacement metal gate, particularly the high-k dielectric (for example, a hafnium oxide liner) of the replacement metal gate. In the prior art, the interfacial oxide layer is formed by, for example, a chemical oxide treatment such as ozone. As shown in FIG. 1, the interfacial chemical oxide (“ChemOx” layer) is formed over the silicon substrate (“Si”). Thereafter, the high-k dielectric (“HfOx”) is deposited, followed by formation of the metal gate (“MG”). However, the resulting interfacial chemical oxide layer is porous and as such is prone to high-k metal incorporation upon the subsequent deposition of the high-k dielectric, thus leading to a diffused junction with the high-k dielectric, as shown in FIG. 1. It is well-known that non-terminated sites in a diffused junction contribute to negative/positive bias temperature instability (NBTI/PBTI) degradation, as further shown in FIG. 1, which causes a loss in device performance. Further, the thickness of the chemical oxide is difficult to control, which leads to the variation of the device performance and reliability problems. It is also difficult to further scale-down device sizes using techniques such as chemical oxidation that are subject to variability.
Accordingly, it is desirable to provide methods for the fabrication of integrated circuits with replacement metal gate structures that provide an improved interfacial oxide layer between the silicon substrate and the replacement metal gate electrode. Particularly, it is desirable to provide methods for the fabrication of nitrated circuits wherein the interfacial oxide layer is not susceptible to high-k dielectric diffusion or temperature stability degradation. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings, the brief summary, and this background of the invention.